This invention relates to array logic and more particularly to cells on such memories which will perform logic functions within the array.
It has been suggested in the past to use multi-state cells to perform logic in either associative or random access arrays. In Gardner et al U.S. Pat. No. 3,543,296 a functional memory employing four state cells is illustrated. These cells are each addressed by a single binary input which is complemented and fed through a mask to the balance bit lines of each cell so as to interrogate the cell for match or no match conditions. With this cell it is possible to store one of four possible states of information; three of which are decipherable in the associative memory configuration. In other words, with a cell in any one of three of the states it is possible to obtain a match condition when that cell is interrogated through the unmasked bit lines of the memory while it is impossible to obtain a match condition if the cell is in the fourth state when it is so interrogated. The three states which are decipherable are called the "zero", the "one" and the "X" or "Don't Care" states. The fourth state or the undecipherable state is referred to as the "Y" state.
Logic is being performed when one of these cells is interrogated for its logic state. Thus the functional memory in the Gardner et al patent is capable of performing logic. However, because only three of four logic states of each cell are decipherable by the configuration, twenty-five percent of the logic power of the array is lost. Furthermore, the four state associative cell configuration can only perform very simple logic functions and to perform higher order logic functions such as an Exclusive OR function requires additional logic circuitry at the output of the memory and/or additional words in the memory. Fleisher et al U.S. Pat. No. 3,593,317 describes a technique using decoders to perform high order logic in ordered arrays and the Weinberger U.S. Pat. No. 3,761,902 applies this technique to functional memories to increase the logic power of such functional memories by minimizing undecipherable states and permitting the performance of higher order logic functions. In the Fleisher et al and Weinberger patents the multiple state cells are either a single multiple state cell or a plurality of bi-stable or quadra-stable cells which are addressed through their bit lines by a decoder for decoding two or more data bits and provide logic results on their output lines. For instance, where a state cell is used only one of the 16 possible states is undecipherable instead of one out of four in the four state cells discussed above. Furthermore, it is possible to perform higher order logic functions such as the Exclusive OR function by using decoders as described in the Fleisher et al and Weinberger patents.
In co-pending application Ser. No. 578,300, filed May 16, 1975, J. W. Jones, "Dynamic Associative Cell", it is suggested that a multiple state logic cell can perform higher order logic functions of the Fleisher et al and Weinberger patents within the array proper and without the use of the multiple bit decoders employed in those patents. The difficulty with this cell is that it requires six input lines; two to carry positive/negative potentials. These input lines require much space on a monolithic chip; therefore, decreasing the density that the cells can be arranged on the chip.